Boundary-Scan test

Vi tror på at Boundary-scan, baseret på IEEE standard 1149.1, er den overlegne teknologi til at løse test og programmerings udfordringer i dagens og morgendagens komplekse elektroniske systemer. Med over 6.000 installationer på verdensplan og branchens stærkeste produktinnovation, er JTAG Technologies ideel til at hjælpe dig realisere fordelene ved Boundary-scan gennem alle faser af produktets livscyklus, fra udvikling til fremstilling af prototyper til produktion til field service.
What is Boundary-scan?

Boundary-scan (also known as JTAG boundary-scan) is a method of testing modern Printed Circuit Boards (PCBs) after assembly. Using the dedicated test logic built into many of today’s integrated circuits (ICs), boundary-scan checks if each device is correctly inserted and soldered onto the PCB.

Typical devices that incorporate boundary-scan technology include CPLDs, FPGAs, microprocessors, DSPs, ASICs, bus logic, SERDES, telecom encoders, PHYs and Bridges (PCI/PCIe).

A number of device manufacturers embracing boundary-scan technology are Intel, Analog Devices, ARM, Freescale, NXP, PLX, ST, TI, Renesas, Xilinx, Altera, Lattice, Broadcom and Actel among others.

In practice
Boundary-scan enabled devices feature four (or sometimes five) dedicated test access port (TAP) signals:
bullet_point_blackTCK (Test Clock)
bullet_point_blackTMS (Test Mode Select)
bullet_point_blackTDI (Test Data In)
bullet_point_blackTDO (Test Data Out)
bullet_point_blackTRST (Test Logic Reset) (optional)

To simplify the test infrastructure within a PCB it is common to connect the devices in a serial (daisy chain) formation so that the first device's TDO connects to the next device’s TDI (and so on) to form a so-called scan chain.

To activate the boundary-scan logic, simply pulse TCK while toggling TMS as specified in the TAP state machine map. Once activated, boundary-scan logic controls the device's pins while isolating the primary core functions of the device.